PRODUCTS 57,58,60 SCRATCH MEMORY DATA
DESC: Screatch memory products: raw counters P57, spin event marker P58, trigger P60
HIST: 03-31-92 JLC Created file
08-26-92 JLC Added support for scratch memory test
09-24-92 JLC Added bypass flag for test after reset (added
SCR_OFF call if memory test is bypassed).
05-12-93 JLC Converted to FM s/w (using new CRTOS)
05-19-93 JLC Cleaned up, final walk-thru - minor mod.s
09-23-93 JLC Fixed some bugs, enabled task (and mem testing)
95-04-04 CAI Add software watchdog. v1.70
96-06-03 CAI Fix reg save errors in BM test. v2.12
96-06-04 CAI Implement H0 burst memory status bits. v2.12
96-06-06 CAI Debug BM_TEST. Still has two problems: 1.
Burst_vcc too low (3.95 V); 2. xio e_R_BM_DATA
instruction in read loop stops all DMA. v2.12
96-06-17 CAI Temporarily rewire Burst_Vcc on EM; now at
4.76 V when on. xio e_R_BM_DATA still
stops all DMA. v2.12
96-08-06 CAI Fixed DB[15:0] bus contention on SCIF/BM
board; now DMA OK. v2.13
96-08-16 CAI Special oscilloscope version of BM_TEST. v2.13
96-09-05 CAI Add address and block tests to BM_TEST.
Add delay after BM power on (at least 100 ms
is needed, depending on hardware). v2.14
96-09-10 CAI Do BMT command verify only for ZEC1SCRS. v2.15
96-09-11 CAI Combine bm_bf and bm_blk_n status bits. v2.15
96-10-16 CAI Add e_SE_BM_CMD error (bad BM cmd); revise
BM command processing. v2.15
96-10-30 CAI Major revision. v2.15
96-12-05 CAI Continue revisions; add e_SE_BMLOST. v2.16
96-12-08 CAI Add burst products P36, P37, and P38. v2.16
96-12-11 CAI Fix INIT_BMR bugs; fix pkt_hdr bugs. v2.17
96-12-12 CAI Add spin_msw to burst status product; fix
CIS2 tlm pkt size bug; fix head ptr wrap
bug in GETB_NULL; started GETB_BLK. v2.17
97-01-10 CAI Finish GETB_BLK; add slow playback test. v2.18
97-01-28 CAI Fix bug which stopped HKP in slow playback
test (save r15 for TLM_TASK in GETB_BLK). v2.19
97-03-27 CAI Change P36 to 16-pkt product; put sweep num
in sequence field. v2.20
02-09-97 AMD Ported the file to Esic.
Increased time-out constant because of the system
higher activity (and sector clock freq.)
Remapped product P36, P37 to P57,P58 and P38 to P60
Redifined completely BT_TLM. Removed Cis-2 related code
09-09-97 AMD Implemented the trigger based on proton density evaluation.
10-09-97 AMD Saved in P60 (trigger product) the current Density trigger
ring. Fixed P6 Density fetching and removed equal
dn conditions in the slope check loops in CHKD_RING $$ 2.27
NOTE: BURST MEMORY ADDRESSING
Burst Memory is 512K 16-bit words. It has nineteen address inputs and sixteen bidirectional data lines. It is addressed by a 19-bit auto-incrementing address register. The address register is initialized by writing a word to e_W_BM_PTR. This clears the low 4 bits of the address register and loads the upper 15 bits of the address register from the low 15 bits of the write data word. (See below.) The 19-bit address register increments by one at the end of each Burst Memory read or write access. The CPU reads a 16-bit word from the Burst Memory at I/O address e_R_BM_DATA and writes a 16-bit word to the Burst Memory at I/O address e_W_BM_DATA. A "chunk" is a 16-word section of Burst Memory starting at address xxxx0h and ending at xxxxFh. The address register always points to the start of a chunk after the upper 15 bits have been loaded by writing xxxxh to e_W_BM_PTR. The word written to e_W_BM_PTR may be thought of as a "chunk pointer".MSb Burst Memory Address Register LSb *--------*-----------*-----------*-----------*------------* | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 | *--------*-----------*-----------*-----------*------------* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ x | | | | | | | | | | | | | | | 0 0 0 0 *-----------*-----------*-----------*------------* | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | *-----------*-----------*-----------*------------* MSb e_W_BM_PTR Write Word LS -----------------------------------------------------------------BURST MEMORY QUEUEThe BM task gets commands and burst packet pointers from the burst memory queue (q_burst). Packet pointers point to RAM (0000-7FFF), so their MSbit is always zero. BM commands in q_burst always have an MSbit of one to distinguish them from packet pointers.BURST MEMORY RELEVANT STATIC DATABurst memory operations (storing/trigger/dumping) are valid only if the current mode is enabled to support the scratch memory operations. The defaults modes enabled for that are listed in the static table at the offset BM_SmM_OM. The table has 16 words size and and each word corresponds to an enabling/disabling flag for the mode number corresponding to the table offset. A `1´ means that SM operation are enabled ´0´ disabled. The default modes
enabled for SM are mode 5 and mode 13.Density evaluation ring has a default deep of 4 densities which can be increased up to 16. Such size is coded at the offset BM_Dnrn_N:
BURST MEMORY STATUS BIT FLAGS
Burst memory activity is synchronized throughout the variable bm_bf which reflect the actual status of the burst memory:
MSb LSb
*---|---|---|---|---|---|---|---|---|---|---|---|---------------*
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
*---|---|---|---|---|---|---|---*---|---|---|---|---------------*
| spare c1 c2 fz su cl ts sp pe pr tg # free blks |
*---|---|---|---|---|---|---|---|---|---|---|---|---------------*IMPORTANT: TLM.ASM assumes sp through tg and # free blocks (b8-b15) appear exactly as shown in low byte.c1 = SM1 (Partition 1) collecting (0=not, 1=collecting) c2 = SM2 (Partition 2) collecting (0=not, 1=collecting) fz = burst memory frozen (0=not, 1=frozen) (SM1 or SM2 or both) su = burst memory collection suspended (0=not, 1=suspended) cl = burst memory collecting (0=not, 1=collecting) ts = test status (0=none, 1=in-progress) sp = scratch memory power (0=off, 1=on) pe = playback enabled (0=disabled, 1=enabled) pr = playback rate (0=HR __$$ BM3, 1=LR __$$slow) tg = burst memory triggered (0=not, 1=triggered) # free blocks: 0 = none (all in use) 1-8 = 1 to 8 64-Kword blocks are free 9-15 = (not used) When burst memory power is off, all bits are zero.P57 Burst Counters productP57 is a 16-Kword product made of sixteen 1024-word packets. Each packet contains the exact copy of the raw counter buffer data collected during one sweep. The 4-bit sequence field in the product header second word gives the sweep number: seq 0 means sweeps 0 ... seq 15 means sweeps 15.COUNTER BUFFERThe counter buffer (ctr_b) supplied by the code in cis.asm is structured as 32 energy sets of 4 mass sets of 8 theta values, as follows:Buffer Theta Offset E-Step Mass (Anode) ------ ------ ---- ----- 0 0 0 0 1 0 0 1 2 0 0 2 ... ... ... ... 7 0 0 7 Masses #1 and #2 8 0 2 0 <--- are out of numer- 9 0 2 1 | ical order in the ... ... ... ... |- buffer. This is 15 0 2 7 | caused by the 16 0 1 0 <--- comparator/counter 17 0 1 1 wiring. ... ... ... ... 30 0 3 6 31 0 3 7 32 1 0 0 33 1 0 1 ... ... ... ... 1021 31 3 5 1022 31 3 6 1023 31 3 7P58 Burst Status ProductP58 is a 11-words product keeping spin info to BETTER time tag the P57 data collected in the burst memory. The first word keeps the MSW of the 32-bit spin counter, the second word the LSW of such spin counter. The third word is the format counter at the time of the spin words sampling. Words 4..15 are just trash and will be available for future releases.
P60 Burst Status ProductP60 is a 48-words product keeping the density ring content which caused the scratch memory to be frozen. The density ring is an evaluation buffer stuffed by the P6 proton momenta computation task at the end of each spin. If such buffer is filled, once per spin the ring is read to see if a positive or a negative trend is found. If a rising or falling edge are detected and the last and the first value are in the ratio greater than 2, the burst memory trigger event is rose . The default density ring size (BM_Dnrn_N) corresponds to 4 density at time (4 float i.e. 8 words plus 3 header words), but can be increased to 16 (i.e. 32 words plus 3 header words) . P60 according to the keeps the copy of the nfo to BETTER time tag the P57 data collected in the burst memory. The first word keeps the MSW of the 32-bit spin counter, the
second word the LSW of such spin counter. The third word is the format counter at the time of the spin words sampling. Words 4..15 are just trash and will be available for future releases.
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